MPI-AMRVAC 3.2
The MPI - Adaptive Mesh Refinement - Versatile Advection Code (development version)
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Modules | Functions/Subroutines
mod_eos_interp.t File Reference

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Modules

module  mod_eos_interp
 Interpolation kernels for the EoS tables (pure math; no EoS state).
 

Functions/Subroutines

pure integer function, public mod_eos_interp::find_index_guard (nodes, n, val, guard, m, scale_m)
 Fast adaptive index lookup. Returns the smallest 1-based ii such that nodes(ii) >= val. Falls back to binary search if the guard array is not built (M = 0). Equivalent in result to find_index_bsearch but O(1) when the guard is present.
 
pure double precision function, public mod_eos_interp::interp_clamped_bilinear_table (vary, varx, table, nx, ny, vmin_y, vmax_y, vmin_x, vmax_x)
 
pure double precision function, public mod_eos_interp::bicubic_lookup (var1, var2, tc)
 Dispatch wrapper: bicubic lookup that branches on the table's is_uniform flag. Hides the uniform-vs-adaptive distinction from call sites – they pass (var1, var2, eos%.
 
pure double precision function, public mod_eos_interp::bilinear_lookup (var1, var2, tc)
 Dispatch wrapper: bilinear lookup that branches on is_uniform.
 
subroutine, public mod_eos_interp::interp_pchip_interleaved (vary, varx, table_il, nq, nx, ny, vmin_y, vmax_y, vmin_x, vmax_x, results)
 Interleaved PCHIP: evaluate N quantities at the same (vary, varx) point. Table layout: table_il(nq, ny, nx) where nq quantities share the same grid. All nq values at each grid point are contiguous in memory (cache-optimal).
 
subroutine, public mod_eos_interp::interp_pchip_interleaved_nu (vary, varx, table_il, nq, nx, ny, var1_nodes, var2_nodes, guard_1, m_1, scale_1, guard_2, m_2, scale_2, results)
 Adaptive-grid sibling of interp_pchip_interleaved. Replaces the affine index calculation (x - x_min) * step_inv with binary searches on the explicit node arrays var{1,2}_nodes (Q axis-1 binary searches: O(log_2 N) comparisons each, total ~16 cmps for N = 256). The PCHIP kernel itself is unchanged: it operates on the local 4-tuple of values regardless of grid spacing. The stride-1 access pattern over the q-slot dimension is preserved, so cache behaviour matches the uniform variant for the inner kernel.
 
subroutine, public mod_eos_interp::precompute_step_inv (tc)